High transient currents during electrostatic discharge (ESD) events can cause damage to core circuits. For protection of core circuits, ESD protection devices can be employed to clamp voltages applied to core circuits to safe, low levels. ESD protection devices can include, e.g., diodes and field effect transistors (FETs).
According to a first approach for ESD protection, an ESD protection device is arranged to operate in a simple turn on mode during an ESD event. At a turn on voltage, voltage across the ESD protection device can be clamped, and the protection device forms a low impedance shunt channel to discharge ESD transients. Current handling ability can be limited by heat generation due to series resistance in the shunting channel. The turn on clamping voltage should be selected to be low enough for protection of a core circuit being protected, but high enough above an operating voltage so as to avoid unintended operation.
According to a second approach for ESD protection, an ESD protection device can be arranged to operate according to a snapback mode of operation during an ESD event. In one example, a FET can be employed to provided snapback mode ESD protection. A FET can define a parasitic bipolar junction transistor (BJT) with a drain defining a parasitic BJT collector, the substrate defining a parasitic BJT base, and the source defining a parasitic BJT emitter. Snapback mode ESD protection can rely on operation of a parasitic BJT transistor defined by a FET.
An ESD protection device can include a first breakdown voltage, known as a triggering voltage, a holding voltage and a second breakdown voltage. An ESD protection device can be designed so that during an ESD event, voltages across the ESD protection device are within a protection region between the holding voltage and the second breakdown voltage.
A FET employed for ESD protection can include a drain (collector) connected to a core circuit I/O contact and a source (emitter) connected to ground. At small ESD voltages, the drain-substrate (collector-base) junction can be reverse biased. As ESD voltages are increased, the first breakdown voltage will be reached. At the first breakdown voltage, known as an avalanche breakdown, there will be a free avalanche of holes/electrons across the drain-substrate (collector-base) junction.
With a reverse bias current flowing into the substrate (base) the parasitic BJT transistor defined by the FET can turn on to discharge the ESD current though a current path from the drain through the substrate to the source (operating as a BJT collector, base and emitter respectively).
Implementing ESD solutions in integrated circuits is always challenging. In one aspect reduced sizes of integrated circuits impose increasing challenges to design of ESD discharge current handling ability of ESD protection devices. Proposals have been made for tuning of ESD snapback operating mode characteristics of an ESD protection device using a drain of special configuration, referred to as an extended drain. However, in integrated circuits, there are significant challenges to realizing extended drain ESD protection devices given that device structure sizes and spacing distances often cannot be varied without costly variations of process flow.